Variable Assignment
A sequential statement which changes the value stored in a variable. A variable assignment has no delay.
Syntax
[Label:] Target := Expression;
Target = {either} VariableName Aggregate
Where
See Sequential Statement
Synthesis
The Expression on the right hand side is synthesized as combinational logic.
The Target is synthesized to a wire, a latch or a flipflop depending on whether the value is stored between clock cycles:
process
variable V, W: Std_logic;
begin
wait until Clock = '1';
V := A nand W; -- a nand gate
V := V nor B; -- a nor gate
W := D; -- a flipflop
S <= V; -- a flipflop
end process;
Example
V := V + 1;
(V, W) := X;
See Also
Variable, Shared Variable, Signal Assignment, Expression
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